Scientists during Oak Ridge National Laboratory and Hypres, a digital superconductor company, have tested a novel cryogenic, or low-temperature, memory dungeon circuit pattern that might boost memory storage while regulating reduction appetite in destiny exascale and quantum computing applications.
The group used Josephson junctions done from niobium and aluminum-based materials, built during Hypres, for a single-bit memory pattern on a chip and demonstrated write, review and reset memory operations occurring on a same circuit. “The exam showed a viability of memory estimate functions to work faster and some-more efficiently,” ORNL’s Yehuda Braiman said.
“This could lead to almost decreased entrance energies and entrance times and concede for some-more circuits to occupy reduction space.” Building on the initial design, ORNL’s Braiman, Niketh Nair and Neena Imam continue operative on multi-valued memory dungeon circuits and vast arrays of memory cells. Their initial step was a ternary memory dungeon circuit design, that was published in Superconductor Science and Technology.
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